1. Signal Integrity
This is the one major issue in VDSM technology and every CAD tool vendor want to address this effectively.
Every CAD tool vendor now is talking about noise analysis, IR drop calculation. Design flows need to address this, if possible prevent or at least fix once the problem surface.
With Oxide thickness decreasing 10 nm in 90 nm technology and expected to touch one molecular layer of oxide (0.2 nm approx.) leakage power is going to play an important role, if not playing already. Gate leakage current density is increasing beyond 1A/cm 2 at 3.0V in 22A 0 thickness. In addition to rapid increase in leakage power, dynamic power is also increasing with the increase in frequency of the device. With this kind of increase in power dissipation, packaging the device is a real challenge, in spite of all measures to control the power.
Some of the well discussed measures to control power:
Note: As the contribution of leakage power to the total power is increasing, Dual Vt (or even tri-Vt) can be very effectively used. We can restrict the low Vt cells only for the critical paths and use high Vt cells for the remaining. (If 100,000 gates consumes 25 mW as leakage power using low Vt, it can be reduced to 1.5 mW using high Vt.)
Chip complexity is increasing with decreasing individual device dimensions. If usable gates in 12mmX12mm silicon area with 130 nm technology were 10 million gates, it is 90 million gates in the same silicon area with 65 nm technology. Imagine its impact on data base size! With more issues to handle in 90nm and beyond, data base can get only get complicated! This is a big challenge to EDA tools and the design managers:
Most of the designs using DSM technology are SOCs with multiple IPs. Testing them can be a time consuming affair. DFT is a must and go beyond scan chains. We can add logic BIST and this will add to the complexity.
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