The IP Modeling tools make it easy to generate, distribute and support robust, simulator-independent models that are derived directly from the design flow — without waiting for first silicon.
IP protection through compilation reduces the source model into binary object code, which for all practical purposes cannot be deciphered and therefore the design source cannot be recovered. It is virtually impossible to reconstruct the source from a binary representation, especially in the case of large models where protection of IP is critical. Model encryption involves the use of a key, leaving open the possibility that a key may be disclosed or discovered in an unauthorized fashion. An encrypted model may be recycled back as input to the same encryption algorithm, thereby creating a secondary output that has no resemblance to the original model. This output may be used or distributed in an unauthorized fashion with little likelihood of the original model owner discovering that the IP is the same in both models, although the forms of representation are different.
The same model will simulate in a variety of simulation environments, simulator languages, simulator versions, hardware platforms and operating systems. Successful, rapid design and verification of complex systems requires access to a wide range of high performance and accurate simulation models of the IP blocks embedded in the design.
Three timing approaches are supported by IP modeling tools:
Gate-level timing can provide more accurate timing representation since the delays are distributed throughout the design and all the internal paths are accurately evaluated. The timing data is protected from being changed by the end user, and therefore this approach may be preferred by model developers who receive the timing data for their model from delay calculators.
Pin-to-pin timing may be less accurate but is faster since only a few top-level delays must be processed.This kind of timing allows the end user to modify the delay values to represent part screening or other non-standard timing versions.
Back-annotation timing allows the model to accurately process the interconnect delays between the model and the rest of the model user’s design. It can be used with either gate-level or pin-to-pin timing, or it can be used by itself.The actual delays for backannotation are provided by the model user based on the specific interconnect delays of their design.
IP modeling tools allow the model user to isolate a model in order to get a simulation trace of that particular model. The test bench is then used to re-run the simulation and debug the model without the need to access the user’s simulation environment or the user’s design. The model developer can plug in an updated model to validate the fixes.
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