Nios Based System Development using SOPC Builder

Introduction

In general, processor based system consists of microprocessor, memory to store the software code (data and instructions), JTAG (to transfer the data from the host machine to the target board) and other components depending on the application.

Nios Processor

Nios II processor is a 32 bit soft core processor provided by the Altera. The Nios II processor has Reduced Instruction Set Computer (RISC) architecture and the architecture uses separate instruction and data buses, which is often referred to as the Harvard architecture. The Nios II architecture supports a flat register file, consisting of thirty two 32-bit general-purpose integer registers and six 32-bit control registers. Nios II processor cores can address a 31-bit address span. The user must assign base address between 0x00000000 and 0x7FFFFFFF.


Fig1: Nios System

SOPC Builder

Altera Quartus II provides a GUI application called SOPC (System on a Programmable Chip) Builder which is used to build an entire system (including processor and other related peripherals) within a couple of minutes. To build a new system, follow the points given below:

  1. Create a new project in Quartus.
  2. Click on the SOPC Builder tab, which is present in the “tools” bar.
  3. Altera provided components (peripherals) are provided on the left side of the window.
  4. Double-click on the Nios II processor. A new window pops up, where the user has the option to choose a particular Nios II core based on the application needs.
  5. This window gives the information on the following parameters:
    • Number of LE’s taken by a particular core.
    • Memory usage of a particular core.
    • Additional hardware properties supported by the different cores.
  6. Once the user clicks the “finish” button, that particular Nios II core is added to the design.
  7. Similarly the user has to add all the components required for his/her system.
  8. SOPC Builder automatically interconnects all the individual components specified using System Interconnect Fabric.
  9. Specify the base addresses and interrupt request priorities of individual components in the system.
  10. The user has to click the “generate” tab after adding all the peripherals. This will generate all the required Verilog or VHDL files for individual modules and a top file will be created which instantiates all the individual files. This top file includes a module called “testbench” which is used to test the system. The user has to modify the “testbench” to suit the requirements.
  11. If “simulation” is also checked in the “System Generation” tab, SOPC Builder generates the required files for modelsim so that the design can be simulated in modelsim along with the software written in Nios II IDE which is explained later. Apart from this, ptf file is created which is used by the software engineer in Nios II IDE which will be discussed later.

SOPC Builder provides a GUI application called “Component Editor” which is used to create user components.


Fig2: Component Editor

  1. In the “HDL Files” tab, the user has to enter all the HDL files (Verilog or VHDL) and should provide the top HDL file.
  2. In the “Signals” tab, the user has to connect the top ports to the processor (if the component has to be connected with the processor) and declare the ports which are to be connected outside the system as “export”.
  3. As the SOPC Builder components follow the Avalon bus, user components should also follow Avalon bus protocol to connect with any of the built in components.
  4. In the “Interface” tab, the user can provide the read or write delay (in clocks or nanoseconds) of the component.

Altera also provides an application called Nios II IDE, which is used by the software engineers to write device driver for the particular system. The IDE provides the environment to write the ‘C’ code, build the project with the given hardware, provides an interface to run on modelsim or on the Instruction Set Simulator (which is the software approach for testing the hardware) and also the mechanism to debug the software code. This way Altera provides a mechanism for system level simulation.

If the user does not have a target board for software development, he/she can run and debug the code with the Nios II instruction set simulator (ISS). The ISS simulates the processor, memory and stdin/stdout/stderr streams which allow you to verify program flow and algorithm correctness. As soon as the user have a target board with an Altera FPGA configured with the Nios II system, he/she can download the software to the board using an Altera download cable, such as the USB-Blaster.

To start working on Nios II IDE, follow the below steps:

  1. From “file” menu, create a new Nios II C/C++ application.
  2. For the “Select Target hardware”, browse to the location where the ptf file is located which was generated in the SOPC Builder.
  3. Provide the file name either use the already existing templates or a blank project and press “next”. Here the user can create a new system library (Board Support Package) or use any system library (if exist).

    Fig3: Nios II IDE
  4. The above figure gives the information about the target hardware, where exactly the different types of memory (Program, data, heap, stack etc) have to be stored and other configuration information. This window is obtained by right clicking the project created above and selecting “System Library Properties”.
  5. If the user wants to test the design in the modelsim environment, then “ModelSim only, no hardware support” to be checked.
  6. Build the project by using the “project” tab and run the design using the “run” tab and selecting “Nios II modelsim”.
  7. If the user is having the hardware board, uncheck the “ModelSim only, no hardware support”, build the project and select run as “Nios II Hardware”.

With Altera’s free Open Core Plus evaluation feature, user can perform the following actions:

  • Simulate the behavior of a Nios II processor within the system.
  • Verify the functionality of the design as well as evaluate its size and speed quickly and easily
  • Generate time-limited device programming files for designs that include Nios II processors
  • Program a device and verify the design in hardware

The user needs to purchase a license for the Nios II processor when he/she is completely satisfied with its functionality and performance and want to take the design to production.

Conclusion

Using the Altera Quartus II software along with Nios II soft processor, SOPC Builder and Nios II IDE, you can program the Altera FPGA or use Modelsim for system level verification.

Feedback

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