PIPE 5.1 VIP

PIPE 5.1 VIP

PIPE 5.1 VIP

Overview

PIPE5.1 verification IP (PIPE5.1 VIP) from Innovative logic is built using UVM methodology with different testcases and with different scenarios. The detailed scenario’s that are verified is mentioned in the document as well as in the verification plan. The main feature of this VIP is the plug and play feature of MAC and SerDes blocks. Plug and play feature is explained below.

  1. VIP for verification of MAC and SerDes
  2. SerDes model would be provided to the customer to very MAC
  3. MAC model would be provided to verify the SerDes model

Verification of MAC & SERDES

In Figure 1, MAC output is driven from the test bench while rest of the other blocks (encoder, decoder, elastic buffer, gearbox and SerDes) would be part of the DUT. You can design their own blocks (encoder, decoder, elastic buffer, gearbox, SerDes) while MAC agent would provide necessary input to encoder and gets data from decoder. Message Bus interface is used for register access status and control registers.

In figure 2, customer SerDes is DUT and the necessary data and power transitions is initiated by MAC agent. Flexibility is provided wherein customer can replace Encoder, Decoder, Gearbox and elastic buffer with their own design or can use innovative logic model.

Verification of MAC

In figure 3, user can connect MAC RTL block having encoder, decoder, gearbox, elastic buffer with SerDes block. SerDes responds to all the commands as per specification of 5.1. This would ensure easy verification of MAC block. The output of SerDes can be connected to Tx and Rx signals of analog block to verify the functionality.

Features

  • VIP for MAC layer/ SerDes.
  • Plug and play feature
  • Support 32GT/s.
  • Message bus interface used to verify PHY/MAC registers.
  • 32-bit parallel interface for transmit and receive PCIE data (MAC and encoder/decoder).
  • Support 128B/130B encoder/decoder.
  • Power states as per PIPE 5.1 specification
  • Mandated “PCLK as PHY input mode” for the operations of PIPE interface.
  • Elastic buffer control
  • Assertions for timing verification of SerDes output
  • 10 bit SerDes data path
  • Loopback by MAC
  • Changing clock rate
  • Power states are verified based on LTSSM
  • Beacon signaling

Coverage:

  • Toggle coverage 100%
  • Code coverage 100%
  • Branch coverage 100%
  • Condition coverage 100%
  • Functional coverage 100%

Deliverable

  • Complete VIP code
  • Test cases
  • Coverage Report
  • User manual

For details, please contact [email protected]

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