Post-Silicon Validation of PCI Express Devices

1. Overview

Validating a high speed interconnect technology like PCI Express is a challenging task. You need to validate the integrity of the physical layer and ensure that reflections, cross-talk, emissions, and other effects are within allowable limits. You also need to validate the interoperability of the physical layer. Tools like Time-domain reflectometry ( TDR) oscilloscopes and multi-port vector network analyzers (VNAs) can be helpful to address some issues. As multi-lane interconnects technology, you also need to check lane-to-lane skew, analyze jitter, and measure drive strength and receiver tolerance. This article tries to highlight the challenges involved in PCI Express Silicon Validation.

2. Physical Layer Validation

Probing PCI Express signals on a printed circuit board or IC package is extremely challenging, because the PCI Express signals are high speed and are differential. A 10+ GHZ flat response differential probe system is needed to achieve this. (Example: Agilent’s The DSO801304A scope and 1169A active differential probe)

Main tasks in this will be:

1. Differential peak-to-peak output voltage measurement
2. Minimum TX (transmitted) eye width
3. Maximum time between the jitter
4. D+/D- (differential plus/differential minus) TX output rise/fall time
5. ac peak common mode output voltage
6. Electrical idle differential peak output voltage
7. Amount of common mode voltage change allowed during receiver detection
8. Creating Time Domain Waveforms to test receiver path
9. Characterizing signal paths: Accuracy and Resolution

3. Data Link Layer Validation

Probing PCI Express signals on a printed circuit board or IC package is extremely challenging, because the PCI Express signals are high speed and are differential. A 10+ GHZ flat response differential probe system is needed to achieve this. (Example: Agilent’s The DSO801304A scope and 1169A active differential probe)

Main tasks in this will be:

1. Differential peak-to-peak output voltage measurement
2. Minimum TX (transmitted) eye width
3. Maximum time between the jitter
4. D+/D- (differential plus/differential minus) TX output rise/fall time
5. ac peak common mode output voltage
6. Electrical idle differential peak output voltage
7. Amount of common mode voltage change allowed during receiver detection
8. Creating Time Domain Waveforms to test receiver path
9. Characterizing signal paths: Accuracy and Resolution

4. Transaction Layer Validation

Transaction layer interfaces with the application software. It initiates request packets and some of them need to be responded with response packets. Same way, it receives response packets and for some of them it responds with request packets. To validate such complex operations, we need packet generators and analyzers. There are few options likeAgilent 16900 Series packet analysis probe , which can automate many compliant testing.

Main tasks involved in transaction layer validation:

• Accepting configuration requests.
• Accepting and rejecting specific fields.
• Payload size validation.
• Handling malformed TLPs.
• ECRC handling.
• Memory read and write request handling, including address formation.
• Interrupt message handling.
• Interpreting Power Management Messages.
• Use of vendor defined messages and ID routing.
• TLP rule checking and reporting.
• Completer generation.
• Read requests with boundary crossing.
• Deadlock handling.

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