USB 3.0 Dual Role Device and Host Controller IP



Innovative Logic USB 3.0 SuperSpeed Dual Role host and device controller IP is compliant with OTG & EH3.0. USB 3.0 dual role IP is able to dynamically swap host/peripheral roles while operating at SuperSpeed using Role Swapping Protocol (RSP) as defined in OTG & EH3.0 specification. The IP is capable of handling multiple devices when acting as Host. USB 3.0 dual role IP has been certified by USB IF and it has been tested with hundreds of available USB 3.0 devices  to ensure full interoperability.  Innovative Logic USB 3.0 dual role IP has been in billions of sockets working seamlessly with many USB 3.0 devices available in the market.


  • Compliant with:
    – USB3.0 specification
    – OTG & EH3.0 specification
    – USB3.0 PIPE interface
    – Support 8/16/32 data bus width
    – AXI, AHB Bus standards
    – Supports 32 bit data bus
  • Supports RSP – Role Swap Protocol and HNP protocol
  • Supports all USB3.0 power down modes
  • Supports Control, Bulk, Isochronous and Interrupt transaction
  • As device configurable up to 15 IN and 15 OUT endpoints apart
    from default endpoint
  • Dynamically configurable Endpoint FIFO for optimum usage
    of memory
  • Synchronous SRAM interface for FIFO
  • Fully integrated DMA controller


Block Diagram

Data Sheet

USB 3.0 Device, Host, OTG IP


  • Synthesizable RTL developed in Verilog HDL
  • Constraints & scripts for synthesis
  • Test bench and Test cases developed in SystemVerilog
  • Sample Driver code
  • User Manual


Target Applications

  • Removable hard disks
  • Digital camera
  • Printer, scanner, etc.
  • Multimedia Applications
  • Mobile phones and Tablets
  • TV, DVD players, Set top Boxes

Functional Description

Port Control State Machine:
This tracks the events at the port for any successful attachment and detachments. This manages both SS and HS/FS ports.

Link Controller:
Link Layer consists of blocks which is responsible for the controlling link and port functionality. All link level protocol controlling is handled by this block. It also has PIPE interface logic. It manages low power mode entry and exits.

Protocol Engine Host and Peripheral function:
This layer handles the USB protocol both in Host and Peripheral mode. In Peripheral mode it handles all the transactions directed towards configured Endpoints. In the Host mode it initiates all the USB transactions. Protocol layer handles concurrent IN and OUT transactions in both Peripheral and Host modes.

DMA Controller:
The core has integrated DMA controller which enables the data transfer between Endpoint Data FIFO and the System Memory. Endpoint Data FIFO is realized using dual port SRAM.

Bus Interface:
System Bus slave interface enables easy integration of core in any system. Bus Master tightly linked to DMA controller enables the DMA to work as Master. Bus interface support AXI/AHB/PLB bus protocols.

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