As designs get complex and grow larger in size, the modeling of these designs using register transfer level languages like Verilog is difficult and overall functionality verification is not possible. System Verilog was developed as an industry standard language to address the functional verification challenges caused by the increasing complexity of designs. System Verilog extends standard Verilog with wide range of constructs and capabilities that enables the comprehensive set of verification methodologies to be implemented with one language. Overall System Verilog is the unified language for both design and verification therefore reduces time for learning different language.
Key SystemVerilog Enhancements for Design
- New hierarchical structure (interface – endinterface) for modeling at higher levels of abstraction. It encapsulates communication and protocol checking within the design eliminating any connection errors. Interface can also be used with clocking blocks to specify timing and modports to specify signal direction. As in Verilog when ever new port is added it has to be included in all the hierarchy of the design which may lead to connection error but with system Verilog interface no need of adding the port in all the related design blocks only added the port in interface and in the design in which the ports is has to be added and also its simple to remove the port also.
- Datatype extensions – SystemVerilog supports the four state (0, 1, x, z) Verilog datatypes and extends it to four/two state logic, bit, int, longint datatypes. Usage of two state (0, 1) data types like bit, int make the simulations run faster. User defined datatypes using typedef, enumerateddatatypes using enum are also supported.
- Supports static variables that are initialized only once if the task or function represents the hardware which is not reentrant task and its variables should be declared as static, and in verification the task or function are reentrant then the task/ function and its variables should be declared as automatic it reinitializes the variable each time task/function is called.
- In Verilog there was no place for Global declarations such as global function used by multiple blocks must be declared in each block and any changes to that function must be made in all related design blocks which may lead to errors still Verilog coding tricks like include files or any other coding tricks can lead to coding error or design maintenance problem. System Verilog enhanced its feature by adding VHDL’s packages. Package definitions are module independent and can be utilized in designs or verification for sharing parameters, data, task, function, and sequence and property declarations within package – endpackage across multiple system Verilog modules, interfaces and programs.
- Supports structures and unions for logical grouping of signals in the design like protocol related signals, state machine signals etc…Verilog did not have convenient mechanism for grouping the signals proper naming conventions was the only one method.
Verilog task and functions enhancements such as arguments can be passed by reference, in automatic functions/tasks. Pass by reference provides the capabilities of Verilog’s external name referencing, without having the limitations of hard coding the external signal. Passing by reference allows a variable to be declared in just the calling scope, and not duplicated within a task or function. The argument direction is declared as a “ref,” instead of input, output or inout. Verilog limitations of hard coded signal names within the task/function does not work well for the multiple use method .This capability of passing value by reference allows to define task/function in a packages and can be imported into any number of design blocks.
- Unpacked arrays where all or part elements of an array can copied to another array unlike Verilog that allows only one element of array to be accessible at a time.Queues are variable size unpacked arrays with variety of built in methods to push/pop elements, insert/delete an elements and to query size etc. Queue resizes automatically and access to any Queue element in constant time index ranges from 0 to $(first to last). In verification queues can be utilized for temporary storage of data and processing, for design queues are not synthesizable dynamic arrays synthesizable.
Key System Verilog Enhancements for Verification
- System Verilog supports Classes an object oriented dynamic data type with following features.
- Used to represent dynamic data objects E.g. network packets, processor instructions etc. Can be created and destroyed dynamically and can be parameterized like modules.
- Encapsulates model behavior Properties hold values and methods implement processing.
- Provides an object-oriented inheritance, Encapsulation, and polymorphism concept for reusability.
- Example: Generation of different packets for different transactions can be done easily by using all the above mentioned features of OOP by the base class defining the Packet structure and the derived classes modifying the same packet according to different Transactions.
- Inter-process synchronization. SystemVerilog provides powerful ways for synchronizing parallel activities within a testbench or abstract model: semaphores, and mailboxes.
A semaphore is a built-in object for synchronizing parallel activities in a testbench. semaphore is arbitration of shared resources (keys) among different processes – if no key is available to a process, it can wait until required number of keys are returned to the bucket Several built-in methods for working with semaphoresare: new(), get(), put() and try_get().
A mailbox is another built-in class that allows messages to be exchanged between processes. A message can be added to the mailbox at anytime by one process, and retrieved anytime later by another process. If there is no message in the mailbox when a process tries to retrieve one, the process can either suspend execution and wait for a message, or continue and check again at a later time.
Mailboxes behave like FIFOs (First-In, First-Out). When the mailbox is created, it can be defined to have a bounded (limited) size, or an unbounded size. If a process tries to place a message into a bounded mailbox that is full, it will be suspended until there is enough room. The mailbox class also provides several built-in methods: new (), put (), try_put (), get (), peek (), try_get () and try_peek ().
- Clocking Block identifies a “clocking domain,” containing a clock signal and the timing and synchronization requirements of the blocks in which the clock is used.
In regular Verilog, which does not have clocking domains, the “initial” procedure have race conditions with the design under test if the design is using the same positive edge of the clock to store values in registers. By using SystemVerilog clocking domain skews, the testbench can reference a clock edge to sample a value or drive stimulus. The appropriate skew will automatically be applied, thus avoiding race conditions with the design. Clocking domains greatly simplify defining a testbench that does not have race conditions with the design being tested.
- Testbench Program Block has special semantics and syntax restrictions to meet the needs of modeling a testbench. A program block:
- Contains a single initial block.
- Executes events in a “reactive phase” of the current simulation time, appropriately synchronized to hardware simulation events.
- Can use a special “$exit” system task that will wait to exit simulation until after all concurrent program blocks have completed execution (unlike “$finish,” which exits simulation immediately).
- Supports dynamic arrays that can be restricted to a particular size during runtime and associative arrays that can be referenced using enum types as values.
- Two random number class rand and randc that aid in constraining the random values generated for verification.
- Constrained randomization Constraints are essential to drive meaningful data in to the design example different packet size, valid address range etc. and allows a test to set the scope for the randomization of objects so that the desired test conditions are generated. In system Verilog constraints are use to control the randomization of random class properties.
- Randomization only occurs when an object’s randomize () method is called.
- Class variables can be declared random using rand and randc keywords. Withrand each generated value is uniformly distributed over all possible combinations and randc (random cyclic) cycles through all values in a random permutation of declared range.
- Using the rand and randc classes and methods, much more elaborate random number generation is possible.
The benefits of constrained random verification are:
- Efficient Test Condition Generation: Constrained random verification compute resources to generate test conditions rapidly.
- Improved Coverage: Constraints allow designers to narrow the scope and focus of random testing to areas that require coverage. This results in tests that go deeper into the state space and offer better functional coverage.
- Creation of complex stimulus: Randomization gives a simulator the freedom to create test conditions which may not have been conceived of by the designer and are time consuming to create manually.
Supports assertions used to check the intent of the design is met over simulation time that can be specified by the design engineer as part of design model or by the verification engineer as part of the test program. There are two types of assertions, immediate and sequential. Immediate assertions execute as a programming statement, similar to anif…else decision. These assertions are simple to use, and can simplify the verification and debug of even simple models.
Sequential assertions execute in parallel with the Verilog code, and evaluate on clock cycles. A sequential assertion is described as a property. A property can span multiple clock cycles, which is referred to as a sequence. SystemVerilog’s PSL-like assertions can describe simple sequences and very complex sequences in short, concise sequence expressions.
Direct Programming Interface (DPI).
System Verilog provides a means for SystemVerilog code to directly call functions written in C, C++ or SystemC, without having to use the complex Verilog Programming Language Interface (PLI). The SystemVerilog DPI provides a bridge between high-level system design using C, C++ or SystemC and lower-level RTL and gate-level hardware design.
Mentioned above the brief overview of SystemVerilog’s enormous features allows modeling and verifying very large designs more easily and verify that these designs are functionally correct with less coding.