USB 3.1 IP SuperSpeedPlus Host Controller IP


USB 3.1 IP SuperSpeedPlus Host controller IP is a standard USB Host controller IP. It is fully compliant with xHCI specification and USB3.1 specification. It is also backward compatible with USB2.0 specification. The Host controller supports all types of USB devices and transactions. It supports multiple root hub ports and capable of handling multiple devices including hubs. Innovative Logic’s Host controller supports many configuration features helping user to mould the IP as per their requirement. Innovative Logic’s Host controller IP supports AXI and AHB system bus interfaces with support to 32/64/128 bit data bus width. The Host controller IP supports PIPE and UTMI interface for easy integration with PHY IP.



  • Compliant with:
    – xHCI specification
    – USB3.1 Gen 2 specification
    – USB3.1 PIPE interface
    – Support 8/16/32 data bus width
    – UTMI interface
    – Support 8/16 data bus width
    – AXI, AHB Bus standards
    – Supports 32/64/128 bit data bus
  • Support multiple root hub ports
  • Support multiple Devices and Endpoints
  • Supports many configuration options
  • Supports all USB3 power down modes
  • Supports all types of US transaction including Bulk Streaming
  • Synchronous SRAM interface for FIFO
  • Fully integrated DMA controller

Block Diagram

Data Sheet

USB 3.1-Host-Datasheet


  • Synthesizable RTL developed in Verilog HDL
  • Constraints & scripts for synthesis
  • Test bench and Test cases developed in SystemVerilog
  • Sample Driver code
  • User Manual

Target Applications

  • Removable hard disks
  • Digital camera
  • Printer, scanner, etc.
  • Multimedia Applications
  • Mobile phones and Tablets
  • TV, DVD players, Set top Boxes

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Additional Resources