Innovative Logic Inc. is a provider of design consulting services. We have a team of highly talented and experienced people. Our mission is to provide complete solutions to ASIC, FPGA, and Embedded System vendors, and drastically reduce their product cost, risk, and time to market. Innovative Logic Inc. offers exciting employment opportunities at its headquarters in Santa Clara, California and in Asia Pacific Design Center, Bangalore, India.
We are seeking for outstanding professionals to join our team. Currently we are looking for people who have experience in the following fields.
If you consider yourself as an expert in any of the above fields and value excellence, partnership and commitment, please send your resume to [email protected] . We are also looking for interns who have are going to complete their degrees soon.
Senior Staff Firmware Engineer (Bangalore, India)
- Manage the team of Engineers as well as play a key role to grow India Design Center
- Highly motivated person who can think out of the box
- Write device drivers, configuring peripherals of complex functions
- Work on industry standard architectures along with peripherals
- Some knowledge of board design
- Porting applications to different operating systems such as Linux
Qualifications
- Good experience in programming languages (C/C++) and operating systems
- Proven experience in designa and development of device drivers
- Exposure to all phases of software development cycles
- Good debugging skills and analytical skills
- Good team player with excellent communication skills
- At least 5 years of related experience in embedded systems
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Senior ASIC Design Engineer (Bangalore, India & Santa Clara, USA)
- Write RTL code in Verilog HDL and/or VHDL
- Develop testbenches at module and chip level
- Create verification plan at module and chip level
- Develop system & chip level test & regression environments using scripts
- Create test cases and run simulations for functional verification, formal verification and code coverage
- Develop High-level Cycle accurate Models
Qualifications
- Expertise in Verilog and / or VHDL
- Proficiency in VERA/SpecMan/SystemC/C++
- Knowledge of Simulation, code coverage tools and assertion tools
- Proficiency in industry standard EDA front tools
- Proficiency in common UNIX scripting languages
- Domain Knowledge: PCI/PCI Express/USB, AMBA AHB/AXI
- Strong communication and problem solving skills
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Design for Test (DFT) Engineer (Santa Clara, USA)
Responsibilities
- Responsible for developing DFT strategies for complex SOC designs
- Capable of resolving scan issue in complex multi-clock domain designs
- Generate & integrate Memory BIST, JTAG, SCAN/ATPG, etc
- Analysis of fault coverage, delay fault, and enhancements
Qualifications
- Experience in developing and running scan insertion scripts
- Performing ATPG simulation & analyzing results
- Excellent debug skills in a Verilog design environment
- Experience with static timing analysis & formal verification
- Direct experience using industry-standard tools such as Verilog, VCS, Tetramax, and FastScan
- Proficiency in common UNIX scripting languages (perl, tcl, csh, sh)
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Staff Circuit Design Engineer (Santa Clara, USA)
Responsibilities
- Responsible for full-chip integration, electrical and timing verification, cell selection and characterization, signal integrity and power analysis
- Circuit simulations, layout extractions, timing characterizations and timing file generations.
- Interfaces with logic, layout and other IC design engineers to meet design goals Performs schematic capture, floorplanning and layout supervision, design verification and documentation
- Understands circuit design flow, from design methodology to CAD tool flow, electrical checks and timing closure
Qualifications
- 4+ years of experience in high performance custom or asic chip design.
- Strong understanding of transistor-level, gate-level and interconnect-level dsm circuit design
- Able to optimize performance, power, reliability and area
- Strong knowledge of hspice, cmos process and layout issues
- Must possess strengths in transistor level circuit design.
- Ability to interface with logic designers and understand verilog.
- Demonstrated ability to work in a team environment
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Staff Physical Design Engineer (Santa Clara, USA)
Responsibilities
- Responsible for all aspects of physical design including timing closure, place and route, clock distribution, IP integration, RC extraction, power and signal integrity analysis, formal verification, DFM, and tapeout.
- Implementation of multimillion gate ASIC designs in the latest technologies
- Meeting highly challenging schedule, performance, and quality constraints.
Qualifications
- 3+ years of experience in large VLSI physical design implementation on 0.15u, 0.13u, or 90 nanometer technology.
- Experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues.
- Expertise in Cadence, Synopsys or Magma physical design tool flow
- Skill and efficiency in scripting using Tcl or perl desirable
- Demonstrated ability to work in a team environment
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Senior FPGA Design Engineer (Santa Clara, USA)
Responsibilities
- Write RTL Code in Verilog / VHDL targeted to the latest FPGA architectures
- Use FPGA features to implement system level functions
- Synthesis and timing closure using industry standard FPGA tools
- Place and Route, bit file generation and targeting design to FPGA.
- Verification and simulation of RTL, Post Synthesis and Post P&R design
Qualifications
- Expertise in Verilog or VHDL language
- Proficiency in one of industry standard FPGA development platforms (Xilinx, Altera, Actel)
- Knowledge of achieving high frequency performance on FPGA
- Knowledge of industry standard simulation tools such as VCS, Modelsim, Verilog-XL, etc.
- Desirable: Knowledge of embedded CPU, high speed I/O, and high speed DSP.
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