ASIC/FPGA Design Verification Services

ASIC/FPGA Design Verification Services

Innovative Logic is a top SoC ASIC/FPGA design and verification services company. Our team can start from spec and take it to silicon on turnkey basis. We also offer onsite and offsite services to our clients globally. We have been offering our services for last 10 years to many clients globally ranging from top 10 semiconductor companies to many startups.

Some of our ASIC design and verification services range from ASIC design, architecture, RTL, OVM/UVM verification to synthesis, STA, DFT, scan, floorplanning, place & route, drc/lvs, GDSII etc. Our FPGA design and emulation services includes FPGA design, emulation, porting, prototyping using latest Altera and Xilinx Methodologies. We also offer analog and mixed signal mask layout services making extensive use of Cadence virtuoso tool. For details about our ASIC and FPGA design and verification services, please click the following links to get more information.

ASIC Design

  • Specification, Architecture, RTL, Synthesis, STA, LEC, Lint
  • Domains: Networking, Storage, Wireless, Video, Bitcoin, Imaging, IOTG, etc.
  • ARM based SOC: ARM7, ARM9, ARM11, Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-R4, Cortex-A5, Cortex-A8, Cortex-A9, Cortex-A15
  • Tools: Verilog-NC, Verilog-XL, QuestaSim, Modelsim, Synopsys Dc, etc.

 

ASIC Verification

  • Methodologies: UVM, OVM, SystemC, C++
  • Tools: QuaestaSim, NC-Verilog, VCS
  • Interfaces: PCIE Gen3/4, USB 3.0/3.1, SATA 3.0, Ethernet, SSD, WIFI, Bluetooth, HDMI, MIPI, Display Port, DDR3, DDR4, QDR
  • Random and direct testing, object Oriented programming, Gate Level simulation, Power aware simulation, RTL versus gates simulation

 

DFT, STA, Synthesis

  • DFT: Scan, ATPG, Test, Fault models. ATE, JTAG, memory BIST, Logic BIST
  • Tools: DFT Compiler, Tetramax, Fastscan, TestCompress
  • STA, Synthesis, Lint: Static Timing Analysis, Synthesis, LEC, CDC
  • Tools: Design Compiler, PrimeTime, Conformal, Spyglass, Physical Compiler

 

RTL to GDSII

  • RTL to GDSII: Synthesis, STA, LEC, physical Synthesis, floorplanning, drc/lvs, place & route
  • Tools: Cadence SOC Encounter (SOCE), Synopsys ICC, Mentor Caliber
  • Technologies: 90nm, 65nm, 40nm, 28nm, 20nm

 

FPGA – Design, Emulation, Porting & Post Silicon Bring up

  • RTL coding, synthesis, floorplanning, Place & Route, emulate compiles SoC design and board bring up
  • Domain: Networking, SSD, Optical, Security, Wireless, Video
  • Tools: Xilinx Vivado, Synopsys Synplify pro & Certify Pro, Altera Quartus II
  • Devices: Altera Stratix, Aria, Cyclone & Xilinx vertex, Spartan, Kintex

 

Analog Mixed Signal & Circuit Design

  • High speed SerDes, Memory controller, PLL, ADC, DAC, Codec, MIPI, Amplifiers
  • Signal integrity, Characterization, Compliance, Board Bring up
  • Simulator: Hspice, verilog-AMS
  • High speed oscilloscope, Logic analyzer

 

Analog & RF Mask Layout

  • Domain: Analog Mixed Signal, RF, High Speed SerDes, DDR3/4, QDR3/4, LPDDR3/4, ADC, DAC, PLL
  • Tools: Cadence virtuoso XL, Caliber, Dracula, Hercules
  • Technology nodes: 90nm, 65nm, 40nm, 28nm, 20nm, CMOS, BiCMOS


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